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True modulo and unsigned right shift. (#10885)

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This commit is contained in:
Redstonneur1256
2025-06-02 20:05:45 +02:00
committed by GitHub
parent f924d0b533
commit ea333a0a63
2 changed files with 4 additions and 0 deletions
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core/src/mindustry/logic/LogicOp.java
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@@ -11,6 +11,7 @@ public enum LogicOp{
div("/", (a, b) -> a / b),
idiv("//", (a, b) -> Math.floor(a / b)),
mod("%", (a, b) -> a % b),
emod("%%", (a, b) -> ((a % b) + b) % b),
pow("^", Math::pow),
equal("==", (a, b) -> Math.abs(a - b) < 0.000001 ? 1 : 0, (a, b) -> Structs.eq(a, b) ? 1 : 0),
@@ -24,6 +25,7 @@ public enum LogicOp{
shl("<<", (a, b) -> (long)a << (long)b),
shr(">>", (a, b) -> (long)a >> (long)b),
ushr(">>>", (a, b) -> (long)a >>> (long)b),
or("or", (a, b) -> (long)a | (long)b),
and("b-and", (a, b) -> (long)a & (long)b),
xor("xor", (a, b) -> (long)a ^ (long)b),